Zahur
Legacy Member
Features for future AMD Microarchitectures
These may be present in the original K8L processors or a more future AMD64 chip, by various reports in the time frame of Q1 07, Q2 07, Q3 07, or for socket AM3 chips, Q1 08; (this variation in reports is probably due to reportings about the same microarchitecture core on different platforms, with each source of these reports only given incomplete information); and K10 microarchitecture in years 2008 to 2009.
* Four processor cores
* independently changeable core voltages
* 48-bit memory addressing for the address BUS of massive memory subsystems
* official support for coprocessors connected via HyperTransport Expansion Slot (HTX)
* Simultaneous DDR2, DDR3 support
* FB-DIMM support in server processors (Opterons)
* Memory mirroring support and RAS
* HyperTransport retry support
* New instructions LZCNT, POPCNT, EXTRQ/INSERTQ, MOVNTSD/MOVNTSS
* More aggressive prefetching (16 bytes to 32 bytes)
* Out of order loads
* Double FP units
* Z-Ram technology, projected to bring 4-5 times the cell density of current SRAM for CPU cache.
* Extension to the AMD64 instruction set during 2007; it is unclear whether AMD plans this for rev. G or rev. H chips.
* Large Level-3 non-inclusive cache, initially expected to be a minimum of 2MB shared cache between processing cores on a single die (each with 512 KB of independent second-level cache).
* Vector coprocessor support, which will bring 1-2 orders of FP/SIMD performance increase if a specialized processor is attached via coherent HyperTransport link in a specialized socket.
* Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket.
* Support for HyperTransport 4.0 at an unspecified date; according to techreport.com[1] and some other sources.
* Increased number of HyperTransport links per processor package to 4 (from 3 in current Opterons), and maximum socket count to 32; this will be implemented in Rev. H Opterons.
* New SIMD instruction set and new, wide SIMD units; in a yet unspecified time frame.
* Implementation and possibly adding extensions of SSE4 , which AMD codenamed SSE4a.
* Possible use of new socket (Socket AM3).
* Contain both DDR2 and DDR3 controllers: AM3 chips to be backward compatible with Socket AM2 motherboards; but socket AM2 chips will not be compatible with AM3 motherboards.
Screen 1
Screen 2
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Roadmaps
1H07:Brisbane--Dual Core--K8L--Socket AM2--65nm Process
2H07
parta--K8L--Socket AM2--65nm Process
Roadmap 1-screen
Roadmap 2-screen
Info slides
Benchmarks
TBA
LINKS--Stories 1/1/2006---???
*"AMD's K8L 65nm core due H1 07", Reg Hardware, 4 April 2006
http://www.reghardware.co.uk/2006/04/04/amd_k8l_roadmap/
* "AMD shows off details of K8L", the INQUIRER, 16 May 2006.
http://www.theinquirer.net/?article=31761
* Anandtech: Fab36 substantially converted to 65 nm by mid-2007
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2734
* the Inquirer: Implementation of FPGA through coherent HTT
http://www.theinquirer.net/default.aspx?article=30539
* LinuxElectrons: AMD demonstrates Hardware Coprocessor Offload
http://www.linuxelectrons.com/article.php/2006032009585692
* Digitimes: Interview with Henri Richard (Part 2)
http://www.digitimes.com/bits_chips/a20060314PR200.html
* the Inquirer: Rev G. and H. AMD64 chips Preliminary information
http://www.theinquirer.net/default.aspx?article=30042
* Geek.com: AMD's K8L to double FPU units in 2007
http://www.geek.com/news/geeknews/2006Jan/bch20060224034964.htm
* Anandtech: AMD CTO speaks about future AMD technologies
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2565
* RealWorldTech: Reporting on AMD Technology Day
http://www.realworldtech.com/page.cfm?ArticleID=RWT060206035626
* PureOC: Reporting on AMD Technology Day
http://www.pureoverclock.com/article37.html
* Arstechnica: AMD K8L and 4X4 Technologies
http://arstechnica.com/news.ars/post/20060602-6977.html
* DailyTech: Socket AM2 Forward Compatible With AM3 CPUs
http://www.dailytech.com/article.aspx?newsid=3169
* theinquirer.net: K8L on schedule, due for release as early as Q1 07
http://theinquirer.net/default.aspx?article=32948
* techreport.com: AMD outlines Future Goals (mostly non-specific at this time)
http://techreport.com/etc/2005q4/amd-direction/index.x?pg=2
* AMD's 65nm Athlon 64 X2 to debut December?
http://www.reghardware.co.uk/2006/05/16/amd_debut_65nm_dec_06/
* AMD's quad-core CPU to consume dual-core power
http://www.tgdaily.com/2006/06/23/amd_quad_core_power/
------------------------------------------------------
Beetje opzoek werk verricht om een beeld te geven wat AMD ons in 2007 zal brengen
Ik zal uiteraard nu en dan updaten!
These may be present in the original K8L processors or a more future AMD64 chip, by various reports in the time frame of Q1 07, Q2 07, Q3 07, or for socket AM3 chips, Q1 08; (this variation in reports is probably due to reportings about the same microarchitecture core on different platforms, with each source of these reports only given incomplete information); and K10 microarchitecture in years 2008 to 2009.
* Four processor cores
* independently changeable core voltages
* 48-bit memory addressing for the address BUS of massive memory subsystems
* official support for coprocessors connected via HyperTransport Expansion Slot (HTX)
* Simultaneous DDR2, DDR3 support
* FB-DIMM support in server processors (Opterons)
* Memory mirroring support and RAS
* HyperTransport retry support
* New instructions LZCNT, POPCNT, EXTRQ/INSERTQ, MOVNTSD/MOVNTSS
* More aggressive prefetching (16 bytes to 32 bytes)
* Out of order loads
* Double FP units
* Z-Ram technology, projected to bring 4-5 times the cell density of current SRAM for CPU cache.
* Extension to the AMD64 instruction set during 2007; it is unclear whether AMD plans this for rev. G or rev. H chips.
* Large Level-3 non-inclusive cache, initially expected to be a minimum of 2MB shared cache between processing cores on a single die (each with 512 KB of independent second-level cache).
* Vector coprocessor support, which will bring 1-2 orders of FP/SIMD performance increase if a specialized processor is attached via coherent HyperTransport link in a specialized socket.
* Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket.
* Support for HyperTransport 4.0 at an unspecified date; according to techreport.com[1] and some other sources.
* Increased number of HyperTransport links per processor package to 4 (from 3 in current Opterons), and maximum socket count to 32; this will be implemented in Rev. H Opterons.
* New SIMD instruction set and new, wide SIMD units; in a yet unspecified time frame.
* Implementation and possibly adding extensions of SSE4 , which AMD codenamed SSE4a.
* Possible use of new socket (Socket AM3).
* Contain both DDR2 and DDR3 controllers: AM3 chips to be backward compatible with Socket AM2 motherboards; but socket AM2 chips will not be compatible with AM3 motherboards.
Screen 1
Screen 2
-----------------------------------------------------------------------
Roadmaps
1H07:Brisbane--Dual Core--K8L--Socket AM2--65nm Process
2H07
parta--K8L--Socket AM2--65nm ProcessRoadmap 1-screen
Roadmap 2-screen
Info slides
Benchmarks
TBA
LINKS--Stories 1/1/2006---???
*"AMD's K8L 65nm core due H1 07", Reg Hardware, 4 April 2006
http://www.reghardware.co.uk/2006/04/04/amd_k8l_roadmap/
* "AMD shows off details of K8L", the INQUIRER, 16 May 2006.
http://www.theinquirer.net/?article=31761
* Anandtech: Fab36 substantially converted to 65 nm by mid-2007
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2734
* the Inquirer: Implementation of FPGA through coherent HTT
http://www.theinquirer.net/default.aspx?article=30539
* LinuxElectrons: AMD demonstrates Hardware Coprocessor Offload
http://www.linuxelectrons.com/article.php/2006032009585692
* Digitimes: Interview with Henri Richard (Part 2)
http://www.digitimes.com/bits_chips/a20060314PR200.html
* the Inquirer: Rev G. and H. AMD64 chips Preliminary information
http://www.theinquirer.net/default.aspx?article=30042
* Geek.com: AMD's K8L to double FPU units in 2007
http://www.geek.com/news/geeknews/2006Jan/bch20060224034964.htm
* Anandtech: AMD CTO speaks about future AMD technologies
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2565
* RealWorldTech: Reporting on AMD Technology Day
http://www.realworldtech.com/page.cfm?ArticleID=RWT060206035626
* PureOC: Reporting on AMD Technology Day
http://www.pureoverclock.com/article37.html
* Arstechnica: AMD K8L and 4X4 Technologies
http://arstechnica.com/news.ars/post/20060602-6977.html
* DailyTech: Socket AM2 Forward Compatible With AM3 CPUs
http://www.dailytech.com/article.aspx?newsid=3169
* theinquirer.net: K8L on schedule, due for release as early as Q1 07
http://theinquirer.net/default.aspx?article=32948
* techreport.com: AMD outlines Future Goals (mostly non-specific at this time)
http://techreport.com/etc/2005q4/amd-direction/index.x?pg=2
* AMD's 65nm Athlon 64 X2 to debut December?
http://www.reghardware.co.uk/2006/05/16/amd_debut_65nm_dec_06/
* AMD's quad-core CPU to consume dual-core power
http://www.tgdaily.com/2006/06/23/amd_quad_core_power/
------------------------------------------------------
Beetje opzoek werk verricht om een beeld te geven wat AMD ons in 2007 zal brengen
Ik zal uiteraard nu en dan updaten!
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